| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 2.00V ~ 5.50V |
| Case/Package | TSSOP-14 |
| Number of Outputs | 4 Output |
| Number of Channels | 4 Channel |
| Number of Bits | 4 Bit |
| Propagation Delay Max (tpd) | 8.50 ns |
| Voltage Nodes | 5.00 V, 3.30 V |
| Number of Gates | 4 Gate |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | 40 ℃ |
| Supply Voltage | 2V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 5.1 mm |
| Size-Width | 4.5 mm |
| Size-Height | 1.05 mm |
| Operating Temperature | -40℃ ~ 125℃ |
description
●The SN74AHC125Q is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.
●To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
●• Q Devices Meet Automotive Performance Requirements
●• Customer-Specific Configuration Control Can Be Supported Along With Major-Change Approval
●• EPIC™ (Enhanced-Performance Implanted CMOS) Process
●• Operating Range 2-V to 5.5-V VCC
●• Latch-Up Performance Exceeds 250 mA Per JESD 17
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