description
●These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs
●• Package Options Include Plastic
● Small-Outline (D) Packages, Ceramic Chip
● Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin PDIP Flip Flop D-Type Pos-Edge 2Element 14Pin PDIP
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin SOIC Flip Flop D-Type Pos-Edge 2Element 14Pin SOIC
TI
TEXAS INSTRUMENTS SN74ALS74AD Flip-Flop, Complementary, Positive Edge, 74ALS74, D, 16ns, 34MHz, 8mA, SOIC
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin SOP T/R
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin SOP
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin SOIC T/R
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin PDIP Tube
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin SOP T/R
TI
Flip Flop D-Type Pos-Edge 2Element 14Pin SOIC T/R
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