The SN74AUP1G125DBVT is a low-power single Bus Buffer Gate with 3-state output. The output is disabled when the output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74AUP1G125 device contains one buffer gate device with output enable control and performs the Boolean function Y = A. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
● Input-disable allows floating input conditions
● IOFF supports partial-power-down mode operation
● Input hysteresis allows slow input transition and better switching noise immunity at input
● 3.6V I/O Tolerant to support mixed-mode signal operation
● 4.6ns maximum at 3.3V Propagation delay (tpd)
● 0.9µA maximum ICC Low static-power consumption
● 4pF typical at 3.3V Cpd Low dynamic-power consumption
● 1.5pF typical CI Low input capacitance
● Low noise - <10% of VCC Overshoot and undershoot
● Green product and no Sb/Br
