| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 145 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 4.50V ~ 5.50V |
| Case/Package | SOP-14 |
| Number of Outputs | 1 Output |
| Output Current | 20.0 mA |
| Number of Circuits | 2 Circuit |
| Clock Speed | 145 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 9.20 ns |
| Voltage Nodes | 5.00 V |
| Output Current Drive | -50.0 µA |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 10.3 mm |
| Size-Width | 5.3 mm |
| Size-Height | 1.95 mm |
| Operating Temperature | 0℃ ~ 70℃ (TA) |
description
●These devices contain two independent positive edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.
●• Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs
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TEXAS INSTRUMENTS SN74F74DR Flip-Flop, Complementary, Differential, Positive Edge, 74F74, D, 9.2ns, 145MHz, 20mA, SOIC
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TEXAS INSTRUMENTS SN74F74N Flip-Flop, Complementary, Positive Edge, 74F74, D, 4.9ns, 100MHz, 20mA, DIP
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Flip Flop D-Type Pos-Edge 2Element 14Pin SOP T/R
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