TYPE | DESCRIPTION |
---|
Mounting Style | Surface Mount |
Frequency | 62.0 MHz |
Number of Pins | 16 Pin |
Supply Voltage (DC) | 2.00V ~ 6.00V |
Case/Package | SOIC-16 |
Number of Outputs | 1 Output |
Number of Circuits | 1 Circuit |
Number of Positions | 16 Position |
Number of Bits | 8 Bit |
Propagation Delay Max (tpd) | 30.0 ns |
Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
Output Current Drive | -1.00 mA |
Number of Inputs | 9 Input |
Operating Temperature (Max) | 85 ℃ |
Operating Temperature (Min) | -40 ℃ |
Supply Voltage | 2V ~ 6V |
Supply Voltage (Max) | 6 V |
Supply Voltage (Min) | 2 V |
TYPE | DESCRIPTION |
---|
Product Lifecycle Status | Active |
Packaging | Each |
Size-Length | 9.9 mm |
Size-Width | 3.91 mm |
Size-Height | 1.58 mm |
Operating Temperature | -40℃ ~ 125℃ |
The SN74HC165DE4 is a 8-bit parallel-load Shift Register that when clocked shift the data toward a serial (QH) output. The parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD\\) input. This device also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. parallel loading is inhibited when SH/LD\ is held high. While SH/LD\ is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH or serial (SER) inputs.
● Outputs can drive up to 10 LSTTL loads
● Complementary outputs
● Direct overriding load (data) inputs
● Gated clock inputs
● Parallel-to-serial data conversion
● 80µA Maximum low power consumption
● 13ns Typical tpd
● ±4mA Output drive at 5V
● 1µA Maximum low input current
● Green product and no Sb/Br
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