| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 29 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 2.00V ~ 6.00V |
| Case/Package | SOIC-14 |
| Number of Outputs | 1 Output |
| Output Voltage | 5.00 V |
| Output Current | 5.2 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 14 Position |
| Clock Speed | 60 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 37.0 ns |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Input Capacitance | 3 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 8.65 mm |
| Size-Width | 3.91 mm |
| Size-Height | 1.58 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74HC74D is a dual positive-edge-triggered D-type Flip-flop with clear and preset. This device contains two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
● Outputs can drive up to 10 LSTTL loads
● 15ns Typical tpd
● Very low input current of 1µA
● ±4mA Output drive at 5V
● 40µA Maximum low power consumption
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