| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 60 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 2.00V ~ 6.00V |
| Case/Package | TSSOP-14 |
| Number of Outputs | 1 Output |
| Output Current | 5.2 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 14 Position |
| Clock Speed | 60 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 37.0 ns |
| Voltage Nodes | 6.00 V, 5.00 V, 2.00 V |
| Input Capacitance | 3 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Width | 4.4 mm |
| Operating Temperature | -40℃ ~ 85℃ |
description/ordering information
●The ’HC74 devices contain two independent D-type positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PREand CLRare inactive (high), data at the data (D) input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
●Wide Operating Voltage Range of 2 V to 6 V
●Outputs Can Drive Up To 10 LSTTL Loads
●Low Power Consumption, 40-µA Max ICC
●Typical tpd = 15 ns
●±4-mA Output Drive at 5 V
●Low Input Current of 1 µA Max
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