| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 25 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 4.75V ~ 5.25V |
| Case/Package | DIP-16 |
| Number of Outputs | 1 Output |
| Output Current | 8 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 16 Position |
| Clock Speed | 33 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 40.0 ns |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 5.00 V |
| Output Current Drive | -50.0 µA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.75V ~ 5.25V |
| Supply Voltage (Max) | 5.25 V |
| Supply Voltage (Min) | 4.75 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.69 mm |
| Size-Width | 6.6 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | 0℃ ~ 70℃ |
The SN74LS109AN is a dual positive-edge-triggered J-K\ Flip-flop with clear and preset. A low level at the preset or clear inputs sets or resets the outputs regardless of the levels of the other inputs. When preset and clear are inactive (high), data at the J and K\ inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the J and K\ inputs may be changed without affecting the levels at the outputs. This flip-flop can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
● TTL Input and output
TI
952 Pages / 47.52 MByte
Motorola
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