SN74LV126APWT Datasheet PDF - TI

The SN74LV126APWT is a quadruple Bus Buffer Gate with 3-state outputs and designed for 2 to 5.5V VCC operation. The LV126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pull-down resistor and the minimum value of the resistor is determined by the current-sourcing capability of the driver.

● IOFF Supports live insertion, partial power down mode and back drive protection

● Support mixed-mode voltage operation on all ports

● Latch-up performance exceeds 100mA per JESD 78, class II

● >2.3V at VCC = 3.3V, TA = 25°C VOHV (Output VOH undershoot)

● <0.8V at VCC = 3.3V, TA = 25°C VOLP (Output ground bounce)

● 6.5ns at 5V Propagation delay (tpd)

● Green product and no Sb/Br