| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 2.00V ~ 5.50V |
| Case/Package | TSSOP-14 |
| Number of Outputs | 1 Output |
| Output Current | 12 mA |
| Number of Circuits | 4 Circuit |
| Number of Positions | 14 Position |
| Number of Bits | 4 Bit |
| Propagation Delay Max (tpd) | 23.0 ns |
| Voltage Nodes | 5.00 V, 3.30 V, 2.50 V |
| Number of Gates | 4 Gate |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 5 mm |
| Size-Width | 4.4 mm |
| Size-Height | 1.15 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The SN74LV132APWR is a quadruple positive-NAND Gate with Schmitt-trigger inputs. The device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. Each circuit functions as a NAND gate, but because of the Schmitt-trigger, it has different input threshold levels for positive- and negative-going signals. The circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
● <0.8V at VCC = 3.3V Typical VOLP (Output ground bounce)
● >2.3V at VCC = 3.3V Typical VOHV (output VOH undershoot)
● Ioff supports live insertion, partial power down mode and back drive protection
● ESD protection exceeds JESD 22
● Latch-up performance exceeds 250mA per JESD 17
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