SN74LV573APW Datasheet PDF - TI

The SN74LV573APW is an octal transparent D-type Latch with 3-state outputs. It is designed for 2 to 5.5V VCC operation. It features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pull-up components.

● Support mixed-mode voltage operation on all ports

● Ioff Supports partial-power-down mode operation

● Latch-up performance exceeds 250mA per JESD 17

● Green product and no Sb/Br