The SN74LVC2G240DCTR is a dual Buffer Driver designed for 1.65 to 5.5V VCC operation. This device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers and bus-oriented receivers and transmitters. This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
● IOFF Supports live insertion, partial-power-down mode and back-drive protection
● Can be used as a down translator to translate inputs from 5.5V down to the VCC level
● Latch-up performance exceeds 250mA per JESD 17
● Inputs accept voltages to 5.5V
● 4.6ns at 3.3V Propagation delay (tpd)
● 10µA ICC Low power consumption
● ±24mA Output drive at 3.3 V
● <0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
● >2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
● Green product and no Sb/Br
