| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Frequency | 150 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 2.00V ~ 3.60V |
| Case/Package | SOIC-14 |
| Number of Outputs | 1 Output |
| Output Current | 24 mA |
| Number of Circuits | 2 Circuit |
| Number of Positions | 14 Position |
| Clock Speed | 150 MHz |
| Number of Bits | 2 Bit |
| Propagation Delay Max (tpd) | 5.20 ns |
| Polarity | Non-Inverting, Inverting |
| Voltage Nodes | 3.30 V, 2.70 V, 2.50 V, 1.80 V |
| Input Capacitance | 5 pF |
| Output Current Drive | -1.00 mA |
| Number of Inputs | 1 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 1.65V ~ 3.6V |
| Supply Voltage (Max) | 3.6 V |
| Supply Voltage (Min) | 1.65 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 8.65 mm |
| Size-Width | 3.91 mm |
| Size-Height | 1.58 mm |
| Operating Temperature | -40℃ ~ 125℃ (TA) |
The SN74LVC74AD is a dual positive-edge-triggered D-type Flip-flop designed for 1.65 to 3.6V VCC operation. A low level at the preset (PRE\\) or clear (CLR\\) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of these devices for down-translation in a mixed-voltage environment.
● Maximum tpd of 5.2ns at 3.3V
● Latch-up performance exceeds 250mA per JESD 17
● Green product and no Sb/Br
TI
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