| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 4.75V ~ 5.25V |
| Case/Package | DIP-16 |
| Number of Outputs | 8 Output |
| Number of Circuits | 3 Circuit |
| Number of Positions | 16 Position |
| Number of Bits | 8 Bit |
| Voltage Nodes | 5.00 V |
| Power Dissipation | 200 mW |
| Bandwidth | 50.0 MHz |
| Output Current Drive | -50.0 µA |
| Number of Inputs | 3 Input |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.75V ~ 5.25V |
| Supply Voltage (Max) | 5.25 V |
| Supply Voltage (Min) | 4.75 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.69 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | 0℃ ~ 70℃ |
The SN74S138AN is a 3-to-8 Decoder/Demultiplexer designed to be used in high-performance memory decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, it can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible. The SN74S138A decode one of eight lines dependent on the conditions at the three binary select inputs and the three enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter.
● Designed specifically for high-speed
● Memory decoders
● Data transmission systems
● 3 Enable inputs to simplify cascading and/or data reception
● Schottky-clamped for high performance
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