TYPE | DESCRIPTION |
---|
Mounting Style | Surface Mount |
Frequency | 2.1 MHz |
Number of Pins | 14 Pin |
Supply Voltage (DC) | 2.00V (min) |
Case/Package | TSSOP-14 |
Supply Current | 360 µA |
Power Dissipation | 0.525 W |
Quiescent Current | 250 µA |
Operating Temperature (Max) | 70 ℃ |
Operating Temperature (Min) | 0 ℃ |
Power Dissipation (Max) | 525 mW |
Supply Voltage | 2V ~ 15V |
Supply Voltage (Max) | 15 V |
Supply Voltage (Min) | 2 V |
TYPE | DESCRIPTION |
---|
Product Lifecycle Status | Active |
Packaging | Tape & Reel (TR) |
Size-Width | 4.4 mm |
Operating Temperature | 0℃ ~ 70℃ |
The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic, and operates at frequencies up to 2 MHz. Because of its high input impedance, this device uses smaller timing capacitors than those used by the NE555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.
●Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.
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