The TMS320C6657CZH is a Digital Signal Processor provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for non-blocking access to all processing cores, peripherals, coprocessors and I/O. This is achieved with four main hardware elements - multicore navigator, TeraNet, multicore shared memory controller and HyperLink. Multicore navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, multicore navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets.
● Multicore shared memory controller (MSMC)
● Memory protection unit for both MSM SRAM and DDR3_EMIF
● 8192 Multipurpose hardware queues with queue manager
● Two Viterbi coprocessors
● One Turbo coprocessor decoder
● Supports direct I/O, message passing
● Single port supporting 1 or 2 lanes
● Supports up to 5GBaud per lane
● Gigabit Ethernet (GbE) subsystem
● Two multichannel buffered serial ports
● Supports connections to other KeyStone architecture devices providing resource scalability
● Green product and no Sb/Br
