TMS320VC5410A Features
●• Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus
●• 40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
●• 17- × 17-Bit Parallel Multiplier Coupled to a 40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
●• Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator
●• Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
●• Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
●• Data Bus With a Bus Holder Feature
●• Extended Addressing Mode for 8M × 16-Bit Maximum Addressable External Program Space
●• 64K x 16-Bit On-Chip RAM Composed of Eight Blocks of 8K × 16-Bit On-Chip Dual-Access Program/Data RAM
●• 16K × 16-Bit On-Chip ROM Configured for Program Memory
●• Enhanced External Parallel Interface (XIO2)
●• Single-Instruction-Repeat and Block-Repeat Operations for Program Code
●• Block-Memory-Move Instructions for Better Program and Data Management
●• Instructions With a 32-Bit Long Word Operand
●• Instructions With Two- or Three-Operand Reads
●• Arithmetic Instructions With Parallel Store and Parallel Load
●• Conditional Store Instructions
