TPS51100EVM-001 Datasheet PDF - TI

The TPS51100EVM evaluation module (EVM) includes an LDO for DDRI and DDRII memory modules with the necessary termination and reference voltages for DDR Memory modules. The EVM is designed to use a 1.5-V to 3.4-V VDDQ voltage and a 4.75 V to 5.25 V controller core supply to generate the necessary ½ VDDQ termination voltage with ± 2-A of sink/source current capacity for dual data rate (DDR) memory modules. The TPS51100EVM allows the user to evaluate the TPS51100 using an external reference voltage or the VDDQ LDO supply voltage to test it with DDRI or DDRII voltage standards and the S3 and S5 sleep states. The TPS51100 is designed to provide proper termination voltage for DDR memory modules covering both states.