TSB41AB1 Datasheet PDF - TI

The TSB41AB1 provides the digital and analog transceiver functions needed to implement a one-port node in a cable-based IEEE 1394 network. The cable port incorporates one differential line transceiver. The transceiver includes circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41AB1 is designed to interface with a link layer controller (LLC), such as the TSB12LV21, TSB12LV22, TSB12LV23, TSB12LV26, TSB12LV31, TSB12LV41, TSB12LV42, or TSB12LV01A.

●The TSB41AB1 requires only an external 24.576-MHz crystal as a reference. An external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal is supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL.

●The TSB41AB1 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in Annex J of IEEE Std 1394-1995 and in IEEE 1394a-2000 (section 5.9.4) (hereinafter referred to as Annex J type isolation). To operate with TI bus holder isolation the ISO\ terminal on the PHY must be high.

●Data bits to be transmitted through the cable port are received from the LLC on two, four or eight parallel paths (depending on the requested transmission speed) and are latched internally in the TSB41AB1 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 393.216 Mbits/s (referred to as S100, S200, and S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information is transmitted differentially on the TPA cable pair.

●During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC.

●Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage.

●The TSB41AB1 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 µF. TPBIAS is typically VDD–0.2 V when the port is not connected to another node.

●The line drivers in the TSB41AB1 operate in a high-impedance current mode, and are designed to work with external 112- resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair-A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair-B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k±1.0%.

●When the power supply of the TSB41AB1 is off while the twisted-pair cables are connected, the TSB41AB1 transmitter and receiver circuitry presents a high impedance to the cable and does not load the TPBIAS voltage at the other end of the cable. Fail-safe circuitry blocks any leakage path from the port back to the device power plane.

●The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD through a 1-k resistor, and SM should be connected directly to ground.

●Four package terminals are used as inputs to set the default value for four configuration status bits in the self-ID packet, and are tied high through a 1-k

●## Features

● Fully Supports Provisions of IEEE 1394-1995 Standard for High Performance Serial Bus† and IEEE 1394a-2000

● Fully Interoperable With FireWire™ and i.LINK™ Implementation of IEEE Std 1394

● Fully Compliant With OpenHCI Requirements

● Provides One IEEE 1394a-2000 Fully Compliant Cable Port at 100/200/400 Megabits Per Second (Mbits/s)

● Full IEEE 1394a-2000 Support Includes: Connection Debounce, Arbitrated Short Reset, Multispeed Concatenation, Arbitration Acceleration, Fly-By Concatenation, Port Disable/Suspend/Resume

● Register Bits Give Software Control of Contender Bit, Power Class Bits, Link Active Control Bit, and IEEE 1394a-2000 Features

● IEEE 1394a-2000 Compliant Common Mode Noise Filter on Incoming TPBIAS

● Extended Resume Signaling for Compatibility With Legacy DV Devices, and Terminal- and Register-Compatibility With TSB41LV01, Allow Direct Isochronous Transmit to Legacy DV Devices With Any Link Layer Even When Root

● Power-Down Features to Conserve Energy in Battery Powered Applications Include: Automatic Device Power Down During Suspend, Device Power-Down Terminal, Link Interface Disable via LPS, and Inactive Ports Powered Down

● Failsafe Circuitry Senses Sudden Loss of Power to the Device and Disables the Port to Ensure That the Device Does Not Load TPBIAS of the Connected Device and Blocks Any Leakage Path From the Port Back to the Device Power Plane

● Software Device Reset (SWR)

● Industry Leading Low Power Consumption

● Ultralow-Power Sleep Mode

● Cable Power Presence Monitoring

● Cable Ports Monitor Line Conditions for Active Connection to Remote Node

● Data Interface to Link-Layer Controller Through 2/4/8 Parallel Lines at 49.152 MHz

● Interface to Link Layer Controller Supports Low Cost TI Bus-Holder Isolation and Optional Annex J Electrical Isolation

● Interoperable With Link-Layer Controllers Using 3.3 V

● Single 3.3-V Supply Operation

● Low-Cost 24.576-MHz Crystal Provides Transmit, Receive Data at 100/200/400 Mbits/s, and Link-Layer Controller Clock at 49.152 MHz

● Low-Cost High-Performance 48/64-Pin TQFP (PHP/PAP) Thermally Enhanced Packages Increase Thermal Performance by up to 210%

● Meets Intel™ Mobile Power Guideline 2000

● Available in 80-Ball, MicroStar Junior™ BGA (GQE) Package

● Available in 64-Ball, Pb-Free, MicroStar Junior™ BGA (ZQE) Package

●FireWire is a trademark of Apple Computer, Incorporated.

●i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.

●Intel is a trademark of Intel Corporation.

●Other trademarks are the property of their respective owners.

●MicroStar Junior is a trademark of Texas Instruments Incorporated.