● Optimized for high-performance 3.3V systems
● 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz
● Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package)
● Pb-free available for all packages
● Lower power operation
● 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
● 3.3V or 2.5V output capability
● Advanced 0.35 micron feature size CMOS FastFLASH technology
● Advanced system features
● In-system programmable
● Superior pin-locking and routability with FastCONNECT II switch matrix
● Extra wide 54-input Function Blocks
● Up to 90 product-terms per macrocell with individual product-term allocation
● Local clock inversion with three global and one product-term clocks
● Individual output enable per output pin with local inversion
● Input hysteresis on all user and boundary-scan pin inputs
● Bus-hold circuitry on all user pin inputs
● Supports hot-plugging capability
● Full IEEE Std 1149.1 boundary-scan (JTAG) support on all devices
● Four pin-compatible device densities
● 36 to 288 macrocells, with 800 to 6400 usable gates
● Fast concurrent programming
● Slew rate control on individual outputs
● Enhanced data security features
● Excellent quality and reliability
● 10,000 program/erase cycles endurance rating
● 20 year data retention
● Pin-compatible with 5V core XC9500 family in common package footprints
