● High-performance CPU with five-stage pipeline
● 12.5 ns instruction cycle at 80 MHz CPU clock (single-cycle execution)
● One-cycle 32-bit addition and subtraction with 40-bit result
● One-cycle multiplication (16 × 16 bit)
● Background division (32 / 16 bit) in 21 cycles
● One-cycle multiply-and-accumulate (MAC) instructions
● Enhanced Boolean bit manipulation facilities
● Zero-cycle jump execution
● Additional instructions to support HLL and operating systems
● Register-based design with multiple variable register banks
● Fast context switching support with two additional local register banks
● 16 Mbytes total linear address space for code and data
● 1024 Bytes on-chip special function register area (C166 Family compatible)
● Interrupt system with 16 priority levels for up to 83 sources
● Selectable external inputs for interrupt generation and wake-up
● Fastest sample-rate 12.5 ns
● Eight-channel interrupt-driven single-cycle data transfer with Peripheral Event Controller (PEC), 24-bit pointers cover total address space
● Clock generation from internal or external clock sources, using on-chip PLL or prescaler
● On-chip memory modules
● 1 Kbyte on-chip stand-by RAM (SBRAM)
● 2 Kbytes on-chip dual-port RAM (DPRAM)
● Up to 16 Kbytes on-chip data SRAM (DSRAM)
● Up to 64 Kbytes on-chip program/data SRAM (PSRAM)
● Up to 768 Kbytes on-chip program memory (Flash memory)
● On-Chip Peripheral Modules
● Two Synchronizable A/D Converters with up to 16 channels, 10-bit resolution, conversion time below 1 µs, optional data preprocessing (data reduction, range check)
● 16-channel general purpose capture/compare unit (CAPCOM2)
● Up to three capture/compare units for flexible PWM signal generation (CCU6x)
● Multi-functional general purpose timer unit with 5 timers -Up to 6 serial interface channels to be used as UART, LIN, high-speed synchronous channel (SPI/QSPI), IIC bus interface (10-bit addressing, 400 kbit/s), IIS interface
● On-chip MultiCAN interface (Rev. 2.0B active) with up to 128 message objects (Full CAN/Basic CAN) on up to 4 CAN nodes and gateway functionality
● On-chip real time clock
● Up to 12 Mbytes external address space for code and data
● Programmable external bus characteristics for different address ranges
● Multiplexed or demultiplexed external address/data buses
● Selectable address bus width
● 16-bit or 8-bit data bus width
● Four programmable chip-select signals
● Single power supply from 3.0 V to 5.5 V
● Programmable watchdog timer and oscillator watchdog
● Up to 75 general purpose I/O lines
● On-chip bootstrap loaders
● Supported by a full range of development tools including C compilers, macroassembler packages, emulators, evaluation boards, HLL debuggers, simulators, logic analyzer disassemblers, programming boards
● On-chip debug support via JTAG interface
● 100-pin Green LQFP package, 0.5 mm (19.7 mil) pitch
