The Z85C3008PSG is a Serial Communications Controller (SCC) with dual-channel, multiprotocol data communications peripheral that easily interfaces with CPU"s with either multiplexed or non-multiplexed address/data buses. It is a pin and software compatible CMOS member of the SCC family introduced by Zilog in 1981. The advanced CMOS process offers lower power consumption, higher performance and superior noise immunity. The programming flexibility of the internal registers allows the SCC to be configured to various serial communications applications. The many on-chip features such as baud rate generators (BRG), digital phase locked loops (DPLL) and crystal oscillators reduce the need for an external logic. Additional features include a 10 x 19-bit status FIFO and 14-bit byte counter to support high speed SDLC transfers using DMA controllers.
● Improve functionality to ease sending back-to-back frames
● Automatic SDLC opening flag transmission
● Automatic Tx underrun/EOM latch reset in SDLC mode
● Automatic RTS deactivation
● TxD Pin forced high in SDLC NRZI mode after closing flag
● Complete CRC reception
● Improved response to abort sequence in status FIFO
● Automatic Tx CRC generator preset/reset
● Extended read for write registers
● Write data set-up timing improvement
● Programmable DTR/REQ timing
● Write data to falling edge of WR setup time requirement is now eliminated
● Reduced INT timing
● Extended read function to read back the written value to the Write registers
● Latching RRO during read
