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ADAU1452 Datasheet - ADI
| Manufacturer: | ADI |
| Description: | SigmaDSP Digital Audio Processor |
| Pictures: |
ADAU1452Datasheet PDF
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ADAU1452/ADAU1451/ADAU1450 Data Sheet
APPLICATIONS INFORMATION
PCB DESIGN CONSIDERATIONS
A solid ground plane is a necessity for maintaining signal integrity
and minimizing EMI radiation. If the PCB has two ground planes,
they can be stitched together using vias that are spread evenly
throughout the board.
Power Supply Bypass Capacitors
Bypass each power supply pin to its nearest appropriate ground
pin with a single 100 nF capacitor and, optionally, with an addi-
tional 10 nF capacitor in parallel. Make the connections to each
side of the capacitor as short as possible, and keep the trace on
a single layer with no vias. For maximum effectiveness, place the
capacitor either equidistant from the power and ground pins or,
when equidistant placement is not possible, slightly nearer to
the power pin (see Figure 81). Establish the thermal connections
to the planes on the far side of the capacitor.
POWER GROUND
TO GROUND
TO POWER
CAPACITOR
11486-087
Figure 81. Recommended Power Supply Bypass Capacitor Layout
Typically, a single 100 nF capacitor for each power ground pin
pair is sufficient. However, if there is excessive high frequency
noise in the system, use an additional 10 nF capacitor in parallel
(see Figure 82). In that case, place the 10 nF capacitor between
the devices and the 100 nF capacitor, and establish the thermal
connections on the far side of the 100 nF capacitor.
VIA TO
POWER PLANE
DVDD
DGND
VIA TO
GROUND PLANE
10nF
100nF
11486-088
Figure 82. Layout for Multiple Power Supply Bypass Capacitors
To provide a current reservoir in case of sudden current spikes,
use a 10 µF capacitor for each named supply (DVDD, AVDD,
PVDD, and IOVDD) as shown in Figure 83.
BULK BYPASS CAPACITORS
3.3V AVDD PVDD IOVDD DVDD
10µF
+
10µF
+
10µF
+
10µF
+
11486-089
Figure 83. Bulk Capacitor Schematic
Parts Placement
Place all 100 nF bypass capacitors, which are recommended for
every analog, digital, and PLL power ground pair, as near as
possible to the ADAU1452/ADAU1451/ADAU1450. Bypass each
of the AVDD, DVDD, PVDD, and IOVDD supply signals on the
board with an additional single bulk capacitor (10 μF to 47 μF).
Keep all traces in the crystal resonator circuit (see Figure 15) as
short as possible to minimize stray capacitance. Do not connect
any long board traces to the crystal oscillator circuit components
because such traces may affect crystal startup and operation.
Grounding
Use a single ground plane in the application layout. Place all
components in an analog signal path away from digital signals.
Exposed Pad PCB Design
The device package includes an exposed pad for improved heat
dissipation. When designing a board for such a package, give
special consideration to the following:
• Place a copper layer, equal in size to the exposed pad, on all
layers of the board, from top to bottom. Connect the copper
layers to a dedicated copper board layer (see Figure 84).
TOP
PO
W
ER
G
R
OU
N
D
BO
TTOM
COPPER SQUARESVIAS
11486-090
Figure 84. Exposed Pad Layout Example—Side View
• Place vias such that all layers of copper are connected,
allowing for efficient heat and energy conductivity. For an
example, see Figure 85, which shows 49 vias arranged in
a 7 × 7 grid in the pad area.
11486-091
Figure 85. Exposed Pad Layout Example—Top View
PLL Filter
To minimize jitter, connect the single resistor and two capacitors
in the PLL filter to the PLLFILT and PVDD pins with short traces.
Rev. C | Page 176 of 180