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SigmaDSP Digital Audio Processor
Silicon Anomaly
ADAU1452
Rev. 0 Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
This anomaly list describes the known bugs, anomalies, and workarounds for the ADAU1452.
Analog Devices, Inc., is committed, through future silicon revisions, to continuously improve silicon functionality. Analog Devices tries
to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended
workarounds outlined here.
ADAU1452 FUNCTIONALITY ISSUES
Silicon Revision Silicon Status Anomaly Sheet No. of Reported Anomalies
C
Release
Rev. 0
1
FUNCTIONALITY ISSUES
Table 1. Failure to Service Interrupt Request [er001]
Background
If a certain interrupt source is active at the same time as a data memory access, there is a chance that the
interrupt request will not be serviced. This can result in a missed audio sample, missed data block, or
communication failure, which can manifest itself as distortion or noise on the audio outputs.
Issue
The failure can occur if at least one interrupt source is active at the same time as a memory access while the DSP
is running.
Interrupt Source used in SigmaStudio Project Memory Access During DSP Operation
Block processing The I
2
C/SPI slave port is used to read from or write to
I
2
C/SPI master control port
The failure is caused when the memory controller attempts to access the memory at the same time as an
interrupt is issued by one of the previously mentioned interrupt sources. In this situation, the memory controller
forces the DSP core clock to stop for 1 clock cycle. If an interrupt request happens during this brief period when
the DSP core clock is stopped, the DSP misses the interrupt, and the interrupt request is cleared, even though the
interrupt service routine was not executed.
Workaround
To avoid this functionality issue, the user must observe at least one of the two following restrictions:
Do not use block processing or the I
2
C/SPI master control port in the SigmaStudio project
Do not access the data memory via the I
2
C/SPI slave control port while the DSP is running
This issue will be resolved in Silicon Revision D. Users must use SigmaStudio release Version 3.10 or later to avoid
this issue, regardless of silicon revision.
Related Issues
None.
SECTION 1. ADAU1452 FUNCTIONALITY ISSUES
Reference Number Description Status
er001 Failure to service interrupt request Resolved in Revision D silicon
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