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EPM7032AETI44-7N Datasheet - Altera
| Manufacturer: | Altera |
| Category: | CPLDs |
| Case Package: | TQFP-44 |
| Description: | CPLD MAX 7000A Family 600Gates 32 Macro Cells 138.9MHz CMOS Technology 3.3V 44Pin TQFP |
| Pictures: |
EPM7032AETI44-7NDatasheet PDF
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Altera Corporation 1
ES-MAXVCCINT-2.0 Preliminary
Errata Sheet
MAX 7000AE, MAX 7000B, &
MAX 3000A Devices
Introduction
This errata sheet provides updated information on MAX
®
7000AE, MAX
7000B, and MAX 3000A devices, addresses known device issues, and
includes workarounds for those issues. Refer to Table 1.
MAX 7000B I/O
Current During
Power
Sequencing
Altera has identified that specific power sequence situations involving
slow rise times on V
CCIO
or I/O pin voltage may cause MAX 7000B I/O
pins to source/sink current before V
CCINT
is ramped. These conditions
can violate the hot-socketing definition which indicates that these pins
should be tri-stated during power-up and should not source/sink more
than 300 μA of current per pin. There are two different power sequence
situations where I/O pins may source or sink current greater than 300 μA.
Table 2 describes the two power sequence issues and their possible
workarounds.
Table 1. MAX 7000AE, MAX 7000B, & MAX 3000A Device Family Issues
Issue Affected Devices
Specific power sequence situations
involving slow rise times for V
CCIO
or I/O
pin voltage can cause I/O source/sink
current greater than 300
μA during
power-up.(1) (2)
MAX 7000B
Fast V
CCINT
rise times may lead to I/O
pin transients during power-up. (1) (2)
MAX 7000AE
MAX 3000A
MAX 7000B
Notes to Ta b le 1 :
(1) MAX 9000, MAX 7000, MAX 7000E, MAX 7000S, MAX 7000A (MAX 7128A and
MAX 7256A) devices are not hot-socket capable devices and, therefore, have an
undefined I/O state during power-up.
(2) Altera is offering permanent recommendations and workarounds for this issue.
December 2005, ver. 2.0
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