| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Case/Package | DIP-16 |
| Number of Circuits | 2 Circuit |
| Clock Speed | 105 MHz |
| Number of Bits | 1 Bit |
| Polarity | Non-Inverting, Inverting |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Rail |
| Size-Length | 19.68 mm |
| Size-Width | 6.6 mm |
| Size-Height | 3.42 mm |
| Operating Temperature | 0℃ ~ 70℃ |
The 74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on S#
●D
●or C#
●D
●prevents clocking and forces Q or Q# HIGH, respectively. Simultaneous LOW signals on S#
●D
●and C#
●D
●force both Q and Q# HIGH
Fairchild
7 Pages / 0.07 MByte
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9 Pages / 0.19 MByte
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