| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 73 MHz |
| Number of Pins | 14 Pin |
| Supply Voltage (DC) | 4.50V (min) |
| Case/Package | DIP |
| Output Current | 4 mA |
| Number of Positions | 14 Position |
| Clock Speed | 66 MHz |
| Number of Bits | 1 Bit |
| Polarity | Non-Inverting, Inverting |
| Number of Gates | 2 Gate |
| Input Capacitance | 3.5 pF |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Each |
| Operating Temperature | -40℃ ~ 125℃ (TA) |
The 74HCT107N is a dual negative edge triggered JK Flip-flop featuring individual J and K inputs, clock (CP\\) and reset (R\\) inputs and complementary Q and Q\ outputs. The reset is an asynchronous active low input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
● TTL Input levels
● Complies with JEDEC standard No. 7A
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