| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 61 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 4.50V (min) |
| Case/Package | DIP |
| Output Current | 4 mA |
| Number of Positions | 16 Position |
| Number of Bits | 2 Bit |
| Polarity | Non-Inverting, Inverting |
| Number of Gates | 2 Gate |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Unknown |
| Packaging | Each |
| Size-Length | 19.5 mm |
| Size-Width | 6.48 mm |
| Size-Height | 3.2 mm |
| Operating Temperature | -40℃ ~ 125℃ |
The 74HCT109N is a positive-edge trigger Dual J K\ Flip-flop with set and reset. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The dual positive-edge triggered J K\ flip-flops with individual J, K\ inputs, clock (CP) inputs, set (SD\\) and reset (RD\\) inputs, also complementary Q and Q\ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K\ inputs control the state changes of the flip-flops as described in the mode select function table. The J and K\ inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. The J K\ design allows operation as a D-type flip-flop by tying the J and K\ inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
● J, K\ Inputs for easy D-type flip-flop
● Toggle flip-flop
● Standard output capability
● ICC Category
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