| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Case/Package | SOIC-20 |
| Output Current | 8 mA |
| Number of Circuits | 8 Circuit |
| Number of Channels | 8 Channel |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Polarity | Non-Inverting |
| Number of Gates | 8 Gate |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 13 mm |
| Size-Width | 7.6 mm |
| Size-Height | 2.35 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The 74VHC573M is an octal high speed CMOS D Latch with 3-state outputs. It is fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type latch is controlled by a LE and an OE\\. When the OE\ input is high, the eight outputs are in a high impedance state. An input protection circuit ensures that 0 to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5 to 3V systems and two supply systems such as battery back-up. This circuit prevents device destruction due to mismatched supply and input voltages.
● Power down protection is provided on all inputs
● High noise immunity
● Low power dissipation
● Pin and function compatible with 74HC573
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