40MX and 42MX FPGA Families
●Features
●High Capacity
●• Single-Chip ASIC Alternative
●• 3,000 to 54,000 System Gates
●• Up to 2.5 kbits Configurable Dual-Port SRAM
●• Fast Wide-Decode Circuitry
●• Up to 202 User-Programmable I/O Pins
●High Performance
●• 5.6 ns Clock-to-Out
●• 250 MHz Performance
●• 5 ns Dual-Port SRAM Access
●• 100 MHz FIFOs
●• 7.5 ns 35-Bit Address Decode
●HiRel Features
●• Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
●• Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
●• QML Certification
●• Ceramic Devices Available to DSCC SMD
●Ease of Integration
●• Mixed-Voltage Operation (5.0V or 3.3V for core and I/Os), with PCI-Compliant I/Os
●• Up to 100% Resource Utilization and 100% Pin Locking
●• Deterministic, User-Controllable Timing
●• Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
●• Low Power Consumption
●• IEEE Standard 1149.1 (JTAG)Boundary Scan Testing
