CD4015 Datasheet PDF - National

General Description

●The CD4015BM/CD4015BC contains two identical, 4-stage, serial-input/parallel-output registers with independent ``Data"", ``Clock,"" and ``Reset"" inputs. The logic level present at the input of each stage is transferred to the output of that stage at each positive-going clock transition. A logic high on the ``Reset"" input resets all four stages covered by that input. All inputs are protected from static discharge by a series resistor and diode clamps to VDDand VSS.

●Features

●Wide supply voltage range 3.0V to 18V

●High noise immunity 0.45 VDD(typ.)

●Low power TTL Fan out of 2 driving 74L

●  compatibility or 1 driving 74LS

●Medium speed operation 8 MHz (typ.) clock rate

●Fully static design @VDD - VSS = 10V