| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 3.00V ~ 18.0V |
| Case/Package | DIP-16 |
| Number of Outputs | 4 Output |
| Number of Positions | 16 Position |
| Clock Speed | 11 MHz |
| Number of Bits | 4 Bit |
| Voltage Nodes | 5.00 V, 10.0 V, 15.0 V |
| Power Dissipation | 500 mW |
| Input Capacitance | 5.00 pF |
| Number of Inputs | 4 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 3V ~ 18V |
| Supply Voltage (Max) | 18 V |
| Supply Voltage (Min) | 3 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Operating Temperature | -55℃ ~ 125℃ |
The CD4516BE is a CMOS presettable binary Up/Down Counter consists of four synchronously clocked D-type flip-flops connected as counters. This counter can be cleared by a high level on the RESET line and can be pre-set to any binary number present on the jam inputs by a high level on the PRESET ENABLE line. If the CARRY-IN input is held low, the counter advances up or down on each positive-going clock transition. Synchronous cascading is accomplished by connecting all clock inputs in parallel and connecting the CARRY-OUT of a less significant stage to the CARRY-IN of a more significant stage. The CD4516B can be cascaded in the ripple mode by connecting the CARRY-OUT to the clock of the next stage. If the UP/DOWN input changes during a terminal count, the CARRY-OUT must be gated with the clock and the UP/DOWN input must change while the clock is high. This method provides a clean clock signal to the subsequent counting stage.
● Synchronous internal carry propagation
● Reset and Preset capability
● 100% Tested for quiescent current at 20V
● Standardized, symmetrical output characteristics
● Meets all requirements of JEDEC tentative standard #13B
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