| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 2.00V (min) |
| Case/Package | DIP-16 |
| Number of Outputs | 8 Output |
| Output Current | 5.2 mA |
| Number of Circuits | 1 Circuit |
| Number of Positions | 16 Position |
| Number of Bits | 8 Bit |
| Bandwidth | 28.0 MHz |
| Output Current (Max) | 4 mA |
| Number of Inputs | 3 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ |
The CD74HC138E is a CMOS high-speed Silicon Gate Decoder well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. Both circuits have three binary select inputs (A0, A1 and A2). If the device is enabled, these inputs determine which one of the eight normally high outputs of the HC138 series will go low. Two active low and one active high enables (E1\, E2\ and E3) are provided to ease the cascading of decoders. The decoder"s 8 outputs can drive 10 low power Schottky TTL equivalent loads.
● I/O port or memory selector
● Three enable inputs to simplify cascading
● Balanced propagation delay and transition times
● Significant power reduction compared to LSTTL logic ICs
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