| TYPE | DESCRIPTION |
|---|
| Mounting Style | Through Hole |
| Frequency | 60 MHz |
| Number of Pins | 16 Pin |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Case/Package | DIP-16 |
| Number of Outputs | 1 Output |
| Output Current | 4 mA |
| Number of Circuits | 2 Circuit |
| Number of Channels | 2 Channel |
| Number of Positions | 16 Position |
| Clock Speed | 60 MHz |
| Number of Bits | 2 Bit |
| Polarity | Non-Inverting, Inverting |
| Input Capacitance | 10 pF |
| Number of Inputs | 2 Input |
| Operating Temperature (Max) | 125 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 19.3 mm |
| Size-Width | 6.35 mm |
| Size-Height | 4.57 mm |
| Operating Temperature | -55℃ ~ 125℃ (TA) |
The CD74HCT112E is a dual negative-edge-triggered J-K Flip-flop with set and reset. It utilizes silicon-gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. It exhibits the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. It has independent J, K, Set, Reset and Clock inputs and Q and Q\ outputs. It changes state on the negative-going transition of the clock pulse. Set and Reset are accomplished asynchronously by low-level inputs. The HCT logic family is functionally as well as pin-compatible with the standard LS logic family.
● Hysteresis on clock inputs for improved noise immunity and increased input rise and fall times
● Asynchronous reset
● Complementary outputs
● Buffered inputs
● Balanced propagation delay and transition times
● Significant power reduction compared to LSTTL logic ICs
● High noise immunity
● Direct LSTTL input logic compatibility
● CMOS Input compatibility
● 15 LSTTL Load bus driver outputs
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