CDCM9102EVM is the evaluation module for CDCM9102, a low jitter clock generator designed to provide reference clocks for communications standards such as PCI Express. The device is easy to configure and use. The CDCM9102 provides two 100MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signalling is supported using an ac coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single ended 25MHz clock output port is provided. Uses for this port include general purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25MHz crystal. This fully assembled and factory tested evaluation board allows complete validation of all device functions.
● Easy to use evaluation module to generate clock signals with low jitter and phase noise
● Easy device setup
● Control pins configurable through jumpers
● Requires 3.3V power supply
● single ended or crystal input clock reference
● Termination available for LVPECL, LVDS, and LVCMOS output clocks
●These devices have limited built in ESD protection. The leads should be shorted together or device placed in conductive foam during storage or handling to prevent electrostatic damage to MOS gates.
