| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 28 Pin |
| Supply Voltage (DC) | 5.00 V, 5.50 V (max) |
| Operating Voltage | 5 V |
| Case/Package | SOIC-28 |
| Supply Current | 50 mA |
| Number of Positions | 28 Position |
| Clock Speed | 70.0 GHz |
| Number of Bits | 8 Bit |
| Access Time | 70 ns |
| Memory Size | 32000 B |
| Access Time(Max) | 70 ns |
| Operating Temperature (Max) | 70 ℃ |
| Operating Temperature (Min) | 0 ℃ |
| Supply Voltage | 4.5V ~ 5.5V |
| Supply Voltage (Max) | 5.5 V |
| Supply Voltage (Min) | 4.5 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tube |
| Size-Length | 18.03 mm |
| Size-Width | 7.62 mm |
| Size-Height | 2.44 mm |
| Operating Temperature | 0℃ ~ 70℃ (TA) |
The CY62256NLL-70SNXC is a 256kB high performance CMOS Static Random Access Memory (SRAM) organized as 32K words by 8-bit. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins is written into the memory location addressed by the address present on the address pins. Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remain inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins.
● High speed - 70ns
● Low active power
● Low standby power
● Easy memory expansion with CE and OE
● TTL-compatible inputs and outputs
● Automatic power-down when deselected
● CMOS for optimum speed/power
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