Part Datasheet Search > EEPROM > Altera > EPCS16SI8N Datasheet PDF > EPCS16SI8N Datasheet Pages 36/40
EPCS16SI8N Datasheet - Altera
| Manufacturer: | Altera |
| Category: | EEPROM |
| Case Package: | SOIC-8 |
| Description: | FPGA Configuration Memory, Flash, 16Mbit, 40MHz, JTAG, Serial, SOIC, 8Pins |
| Pictures: |
EPCS16SI8NDatasheet PDF
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Page 36 Pin Information
Serial Configuration (EPCS) Devices Datasheet April 2014 Altera Corporation
Table 23 lists the pin description of the EPCS device.
Table 23. EPCS Device Pin Description
Pin
Nam
e
Pin Number
i
n 8-Pin
SOIC
Package
Pin Number
in 16-Pin
SOIC
Package
Pin Type Description
DATA
2 8 Output
The
DATA
output signal transfers data serially out of the EPCS device
to the FPGA during the read operation or configuration. During the
read operation or configuration, the EPCS device is enabled by pulling
the
nCS
signal low. The
DATA
signal transitions on the falling edge of
the
DCLK
signal.
ASDI
5 15 Input
The
ASDI
signal is used to transfer data serially into the EPCS device.
This pin are also receiving data that are programmed into the EPCS
device. Data is latched on the rising edge of the
DCLK
signal.
nCS
1 7 Input
The
nCS
signal toggles at the beginning and the end of a valid
instruction. When this signal goes high, the device is deselected and
the
DATA
pin is tri-stated. When this signal goes low, the device is
enabled and in an active mode. After power up, the EPCS device
requires a falling edge on the
nCS
signal before the EPCS device
begins any operation.
DCLK
6 16 Input
The FPGA provides the
DCLK
signal. This signal provides the timing
for the serial interface. The data presented on the
ASDI
pin is latched
to the EPCS device on the rising edge of the
DCLK
signal. The data on
the
DATA
pin changes after the falling edge of the
DCLK
signal and is
latched into the FPGA on the next falling edge of the
DCLK
signal.
V
CC
3, 7, 8 1, 2, 9 Power Connect the power pins to a 3.3-V power supply.
GND
4 10 GND Ground pin.
Figure 23 shows the layout recommendation for vertical migration from the EPCS1
device to the EPCS128 device.
Figure 23. Layout Recommendation for Vertical Migration from the EPCS1 Device to the EPCS128
Device
Pin 1 ID
Pin 1 ID
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