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SCANSTA112
SNLS161I –DECEMBER 2002–REVISED APRIL 2013
www.ti.com
PIN DESCRIPTIONS
No.
Pin Name Pins I/O Description
VCC 10 N/A Power
GND 10 N/A Ground
RESET 1 I RESET Input: will force a reset of the device regardless of the current state.
ADDMASK 1 I ADDRESS MASK input: Allows masking of lower slot input pins.
MPsel
B1/B0
1 I MASTER PORT SELECTION: Controls selection of LSP
B0
or LSP
B1
as the backplane port. The
unselected port becomes LSP
00
. A value of "0" will select LSP
B0
as the master port.
SB/S 1 I Selects ScanBridge or Stitcher Mode.
LSPsel
(0-6)
7 I In Stitcher Mode these inputs define which LSP's are to be included in the scan chain
TRANS 1 I Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit of the
control register at power-up. This value is used to control the presence of registers and pad-bits in
the scan chain while in the stitcher mode.
TLR_TRST 1 I Sets the driven value of TRST
0-5
when LSP TAPs are in TLR and the device is not being reset.
During RESET = "0" or TRST
B
= "0" (IgnoreReset = "0") TRST
n
= "0". This pin is to be tied low to
match the function of the SCANSTA111
TLR_TRST
6
1 I This pin affects TRST of LSP
6
only. This pin is to be tied low to match the function of the
SCANSTA111
TDI
B0
, TDI
B1
2 I BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the 'STA112 through this
input pin. MPsel
B1/B0
determines which port is the master backplane port and which is LSP
00
. This
input has a 25KΩ internal pull-up resistor and no ESD clamp diode (ESD is controlled with an
alternate method). When the device is power-off (V
DD
floating), this input appears to be a capacitive
load to ground
(1)
. When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears to be a
capacitive load with the pull-up to ground.
TMS
B0
, TMS
B1
2 I/O BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the
'STA112. Also controls sequencing of the TAPs which are on the local scan chains. MPsel
B1/B0
determines which port is the master backplane port and which is LSP
00
. This bidirectional TRI-
STATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no ESD clamp
diode (ESD is controlled with an alternate method). When the device is power-off (V
DD
floating), this
input appears to be a capacitive load to ground
(1)
. When V
DD
= 0V (i.e.; not floating but tied to V
SS
)
this input appears to be a capacitive load with the pull-up to ground.
TDO
B0
, TDO
B1
2 I/O BACKPLANE TEST DATA OUTPUT: This output drives test data from the 'STA112 and the local
TAPs, back toward the scan master controller. This bidirectional TRI-STATE pin has 12mA of drive
current. MPsel
B1/B0
determines which port is the master backplane port and which is LSP
00
. Output
is sampled during interrogation addressing. When the device is power-off (V
DD
= 0V or floating), this
output appears to be a capacitive load
(1)
.
TCK
B0
, TCK
B1
2 I/O TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls all
scan operations of the 'STA112 and of the local scan ports. MPsel
B1/B0
determines which port is the
master backplane port and which is LSP
00
. These bidirectional TRI-STATE pins have 24mA of drive
current with hysterisis. This input has no pull-up resistor and no ESD clamp diode (ESD is controlled
with an alternate method). When the device is power-off (V
DD
floating), this input appears to be a
capacitive load to ground
(1)
. When V
DD
= 0V (i.e.; not floating but tied to V
SS
) this input appears to
be a capacitive load to ground.
TRST
B0
, TRST
B1
2 I/O TEST RESET: An asynchronous reset signal (active low) which initializes the 'STA112 logic.
MPsel
B1/B0
determines which port is the master backplane port and which is LSP
00
. This
bidirectional TRI-STATE pin has 24mA of drive current, with a 25KΩ internal pull-up resistor and no
ESD clamp diode (ESD is controlled with an alternate method). When the device is power-off (V
DD
floating), this pin appears to be a capacitive load to ground
(1)
. When V
DD
= 0V (i.e.; not floating but
tied to V
SS
) this input appears to be a capacitive load with the pull-up to ground.
TRIST
B0
, TRIST
B1
, 5 O TRI-STATE NOTIFICATION OUTPUT: This signal is asserted high when the associated TDO is
TRIST
(01-03)
TRI-STATEd. Associated means TRIST
B0
is for TDO
B0
, TRIST
01
is for TDO
01
, etc. This output has
12mA of drive current.
A0
B0
, A1
B0
, A0
B1
, 4 I BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y
n
of a
A1
B1
single selected LSP. (Not available when multiple LSPs are selected). This input has a 25KΩ
internal pull-up resistor. MPsel
B1/B0
determines which port is the master backplane port and which is
LSP
00
.
Y0
B0
, Y1
B0
, Y0
B1
, 4 O BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from the A
n
of
Y1
B1
a single selected LSP. (Not available when multiple LSPs are selected). This TRI-STATE output has
12mA of drive current. MPsel
B1/B0
determines which port is the master backplane port and which is
LSP
00
.
(1) Refer to the IBIS model on our website for I/O characteristics.
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