General Description
●The DS90CR217 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 21 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data through put is 1.785 Gbit/s (223 Mbytes/sec).
●The narrow bus and LVDS signalling of the DS90CR217 is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
●Features
●■ 20 to 85 MHz shift clock support
●■ 50% duty cycle on receiver output clock
●■ Best-in-Class Set & Hold Times on TxINPUTs
●■ Low power consumption
●■ ±1V common-mode range (around +1.2V)
●■ Narrow bus reduces cable size and cost
●■ Up to 1.785 Gbps throughput
●■ Up to 223 Mbytes/sec bandwidth
●■ 345 mV (typ) swing LVDS devices for low EMI
●■ PLL requires no external components
●■ Rising edge data strobe
●■ Compatible with TIA/EIA-644 LVDS standard
●■ Low profile 48-lead TSSOP package
