| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 6 Pin |
| Case/Package | SC-70-6 |
| Number of Positions | 6 Position |
| Drain to Source Resistance (on) (Rds) | 4 Ω |
| Power Dissipation | 0.3 W |
| Threshold Voltage | 850 mV |
| Drain to Source Voltage (Vds) | 25 V |
| Rise Time | 4.5 ns |
| Input Capacitance (Ciss) | 9.5pF @10V(Vds) |
| Input Power (Max) | 300 mW |
| Fall Time | 3.2 ns |
| Operating Temperature (Max) | 150 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| Power Dissipation (Max) | 300 mW |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2 mm |
| Size-Width | 1.25 mm |
| Size-Height | 1 mm |
| Operating Temperature | -55℃ ~ 150℃ (TJ) |
The FDG6301N is a dual N-channel logic level enhancement-mode Digital FET with high cell density and DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. It has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signals MOSFETs.
● Very low level gate drive requirements allowing direct operation in 3V circuits (VGS (th) <1.5V)
● Gate-source Zener for ESD ruggedness (>6kV human body model)
● Compact industry standard surface-mount-package
ON Semiconductor
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ON Semiconductor
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