| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 6 Pin |
| Current Rating | 500 mA |
| Case/Package | SC-70-6 |
| Drain to Source Resistance (on) (Rds) | 0.45 Ω |
| Polarity | N-Channel, P-Channel |
| Power Dissipation | 300 mW |
| Threshold Voltage | 800 mV |
| Input Capacitance | 62.0 pF |
| Gate Charge | 1.10 nC |
| Drain to Source Voltage (Vds) | 25 V |
| Breakdown Voltage (Drain to Source) | 25.0 V |
| Breakdown Voltage (Gate to Source) | ±8.00 V |
| Continuous Drain Current (Ids) | 410 mA |
| Rise Time | 8.00 ns |
| Input Capacitance (Ciss) | 50pF @10V(Vds) |
| Input Power (Max) | 300 mW |
| Operating Temperature (Max) | 150 ℃ |
| Operating Temperature (Min) | -55 ℃ |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Tape & Reel (TR) |
| Size-Length | 2 mm |
| Size-Width | 1.25 mm |
| Size-Height | 1.1 mm |
| Operating Temperature | -55℃ ~ 150℃ (TJ) |
The FDG6321C is a dual N/P-channel logic level enhancement-mode MOSFET with high cell density and DMOS technology. This very high density process is especially tailored to minimize ON-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.
● Very small package outline
● Very low level gate drive requirements allowing direct operation in 3V circuits (VGS (th) <1.5V)
● Gate-source Zener for ESD ruggedness
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