HEF4516BT,652 Datasheet PDF - NXP

The HEF4516BT is a 4-bit edge-triggered synchronous Binary Up/Down Counter with a clock input, an up/down count control input (UP/DN\\), an active low count enable input (CE\\), an asynchronous active high parallel load input (PL), four parallel inputs (D0 to D3), four parallel outputs (Q0 to Q3), an active low terminal count output (TC\\) and an overriding asynchronous master reset input (MR). Information on D0 to D3 is loaded into the counter while PL is high, independent of all other input conditions except for MR which must be low. When PL and CE are low, the counter changes on the low-to-high transition of clock. Input UP/DN\ determine the direction of the count, counting up when high and counting down when low. When counting up, TC\ is low when Q0 and Q3 are high and CE\ is low. When counting down, TC\ is low when Q0 to Q3 and CE\ are low. A high on MR resets the counter (Q0 to Q3 = low) independent of all other input conditions.

● Fully static operation

● Standardized symmetrical output characteristics

● Complies with JEDEC standard JESD 13-B