HEF4520BT Datasheet PDF - NXP

The HEF4520BT is a 4-bit dual internally synchronous Binary Counter has an active high clock input (nCP0) and an active low clock input (nCP1\\), buffered outputs from all four bit positions (nQ0 to nQ3) and an active high overriding asynchronous master reset input (nMR). The counter advances on either the low-to-high transition of the nCP0 input if nCP1\ is high or the high-to-low transition of the nCP1\ input if nCP0 is low. Either nCP0 or nCP1\ may be used as the clock input to the counter while the other clock input may be used as a clock enable input. Schmitt trigger action makes the clock input highly tolerant of slower clock rise and fall times. A high on nMR resets the counter (nQ0 to nQ3 = low) independent of nCP0 and nCP1\\. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.

● Tolerant of slow clock rise and fall time

● Fully static operation

● Standardized symmetrical output characteristics

● Complies with JEDEC standard JESD 13-B