● Processor core
● ARM Cortex-M3 processor (version r2p1), running at frequencies of upto 180 MHz
● ARM Cortex-M3 built-in Memory Protection Unit (MPU) supporting eightregions
● ARM Cortex-M3 built-in Nested Vectored Interrupt Controller(NVIC)
● Non-maskable Interrupt (NMI) input
● JTAG and Serial Wire Debug serial trace, eight breakpoints, and fourwatch points
● Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB)support
● System tick timer
● On-chip memory
● 200 kB SRAM for code and data use
● Multiple SRAM blocks with separate bus access
● 64 kB ROM containing boot code and on-chip software drivers
● 64 bit + 256 bit One-Time Programmable (OTP) memory forgeneral-purpose use
● Clock generation unit
● Crystal oscillator with an operating range of 1 MHz to 25 MHz
● 12 MHz internal RC oscillator trimmed to 1.5 % accuracy overtemperature and voltage
● Ultra-low power RTC crystal oscillator
● Three PLLs allow CPU operation up to the maximum CPU rate without theneed for a high-frequency crystal. The second PLL is dedicated tothe High-speed USB, the third PLL can be used as audio PLL.
● Clock output
● Configurable digital peripherals:
● State Configurable Timer (SCTimer/PWM) subsystem on AHB
● Global Input Multiplexer Array (GIMA) allows to cross-connectmultiple inputs and outputs to event driven peripherals like timers,SCTimer/PWM, and ADC0/1
● Serial interfaces:
● Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at ratesof up to 52 MB per second
● 10/100T Ethernet MAC with RMII and MII interfaces and DMA support forhigh throughput at low CPU load. Support for IEEE 1588 timestamping/advanced time stamping (IEEE 1588-2008 v2)
● One High-speed USB 2.0 Host/Device/OTG interface with DMA support andon-chip high-speed PHY (USB0)
● One High-speed USB 2.0 Host/Device interface with DMA support,on-chip full-speed PHY and ULPI interface to an external high-speedPHY (USB1).
● USB interface electrical test software included in ROM USB stack
● Four 550 UARTs with DMA support: one UART with full modem interface;one UART with IrDA interface; three USARTs support UART synchronousmode and a smart card interface conforming to ISO7816specification
● Up to two C_CAN 2.0B controllers with one channel each. Use of C_CANcontroller excludes operation of all other peripherals connected tothe same bus bridge
● Two SSP controllers with FIFO and multi-protocol support. Both SSPswith DMA support
● One Fast-mode Plus I²C-bus interface with monitor mode andwith open-drain I/O pins conforming to the full I²C-busspecification. Supports data rates of up to 1 Mbit/s.
● One standard I²C-bus interface with monitor mode andstandard I/O pins
● Two I²S interfaces with DMA support, each with one inputand one output.
● Digital peripherals:
● External Memory Controller (EMC) supporting external SRAM, ROM, NORflash, and SDRAM devices
● LCD controller with DMA support and a programmable display resolutionof up to 1024 H x 768 V. Supports monochrome and color STN panelsand TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table(CLUT) and 16/24-bit direct pixel mapping
● Secure Digital Input Output (SD/MMC) card interface
● Eight-channel General-Purpose DMA controller can access all memorieson the AHB and all DMA-capable AHB slaves
● Up to 164 General-Purpose Input/Output (GPIO) pins with configurablepull-up/pull-down resistors
● GPIO registers are located on the AHB for fast access. GPIO portshave DMA support
