Overview
●Based on the ARM Cortex-M0+ core, LPC84x is a low-cost, 32-bit MCU family operating at frequencies of up to 30 MHz. The LPC84x MCU family supports up to 64 KB of flash memory and 16 KB of SRAM.
●This family features exceptional power efficiency in low-current mode using the FRO as the clock source. The peripheral complement of the LPC84x MCU family includes a CRC engine, four I2C-bus interfaces, up to five UARTs, up to two SPI interfaces, capacitive touch interface (enablement coming in Q3), one multi-rate timer, self-wake-up timer, SCTimer/PWM, one general purpose 32-bit counter/timer, a DMA, one 12-bit ADC, two 10-bit DACs, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 54 general-purpose I/O pins.
●MoreLess
●## Features
● Low power, simple, flexible and small form factor
● Low-power, 30 MHz ARM Cortex-M0+ core with advanced power optimization
● Advanced peripherals for full range of timing functionality and design flexibility
● Best-in-class serial connectivity
● Small footprint in popular packages
● Exceptional power efficiency in low-current mode using the FRO as the clock source
● Free Running Oscillator (FRO)
● Five power modes
● Power profile APIs for simple runtime power optimization
● More memory
● 64 kB Flash, small 64 B page size suitable for EEPROM emulation
● 16 kB RAM (Logic for Bit banding across all of SRAM)
● FAIM is used to configure the part at start-up
● Pin configuration including direction and pull-up or pull-down
● Clocks and PMU for low-power start-up
● Full range of timing features from basic to advanced (SCTimer/PWM)
● Flexible triggers to optimize power use
● Accurate 1.2-Msps ADC: 12 ch, 12-bit
● Ideal for oversampling to improve conversion accuracy
● Digital-to-Analog Converter (DAC) : 2 ch, 10-bit
● Capacitive touch interface (enablement coming in Q3)
● More serial connectivity
● 4 I2C for digital sensor interface and more
● 2 SPI, 5 UART
● 54 GPIO with switch matrix, support input pattern match engine
● 25-ch DMA offloads core
●## Features
