TYPE | DESCRIPTION |
---|
Mounting Style | Surface Mount |
Number of Pins | 5 Pin |
Supply Voltage (DC) | 5.00 V |
Operating Voltage | 3.0V ~ 5.5V |
Case/Package | TSOT-23-5 |
Halogen Free Status | Halogen Free |
Number of Outputs | 1 Output |
Supply Current | 40 μA |
Number of Circuits | 1 Circuit |
Number of Channels | 1 Channel |
Number of Positions | 5 Position |
Number of Bits | 1 Bit |
Power Dissipation | 200 mW |
Number of Inputs | 1 Input |
Operating Temperature (Max) | 125 ℃ |
Operating Temperature (Min) | -55 ℃ |
Power Dissipation (Max) | 200 mW |
Supply Voltage | 3V ~ 5.5V |
Supply Voltage (Max) | 5.5 V |
Supply Voltage (Min) | 3 V |
TYPE | DESCRIPTION |
---|
Product Lifecycle Status | Active |
Packaging | Tape & Reel (TR) |
Size-Length | 3 mm |
Size-Width | 1.5 mm |
Size-Height | 1 mm |
Operating Temperature | -55℃ ~ 125℃ |
The M74VHC1GT125DT1G is a single gate non-inverting Buffer/CMOS Logic Level Shifter fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent bipolar Schottky TTL while maintaining CMOS low power dissipation. It requires the 3-state control input (OE) to be set high to place the output into the high impedance state. The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3V CMOS logic to 5V CMOS Logic or from 1.8V CMOS logic to 3V CMOS Logic while operating at the high-voltage power supply. The input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the buffer to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V.
● Power down protection provided on inputs and outputs
● Balanced propagation delays
● Pin and function compatible with other standard logic families
● LSTTL-Compatible inputs
● 62 FETs and 16 equivalent gates chip complexity
● High speed - Propagation delay (tpd) = 3.5ns typical at VCC = 5V
● Low power dissipation - ICC = 1µA maximum at TA = 25°C
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Buffer/Line Driver 1CH Non-Inverting 3-ST CMOS 5Pin TSOP T/R
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