| TYPE | DESCRIPTION |
|---|
| Mounting Style | Surface Mount |
| Number of Pins | 20 Pin |
| Digital Logic Level | CMOS |
| Supply Voltage (DC) | 5.00 V, 6.00 V (max) |
| Case/Package | SOIC-20 |
| Number of Outputs | 8 Output |
| Output Current | 7.8 mA |
| Number of Circuits | 8 Circuit |
| Number of Channels | 8 Channel |
| Number of Positions | 20 Position |
| Number of Bits | 8 Bit |
| Polarity | Non-Inverting |
| Quiescent Current | 80 µA |
| Number of Gates | 8 Gate |
| Number of Inputs | 8 Input |
| Operating Temperature (Max) | 85 ℃ |
| Operating Temperature (Min) | -40 ℃ |
| Supply Voltage | 2V ~ 6V |
| Supply Voltage (Max) | 6 V |
| Supply Voltage (Min) | 2 V |
| TYPE | DESCRIPTION |
|---|
| Product Lifecycle Status | Active |
| Packaging | Each |
| Size-Length | 13 mm |
| Size-Width | 7.6 mm |
| Size-Height | 2.35 mm |
| Operating Temperature | -40℃ ~ 85℃ |
The MM74HC573WM is a 3-state high speed octal D Latch utilizes advanced silicon-gate P-well CMOS technology. It possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-state feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LE input is high, the Q outputs will follow the D inputs. When the LE goes low, data at the D inputs will be retained at the outputs until LE returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The 74HC logic family is speed, function and pinout compatible with the standard 74LS logic family.
● Compatible with bus-oriented systems
● Output drive capability - 15 LS-TTL loads
● 1µA Maximum low input current
● 80µA Maximum low quiescent current
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