The PC16552DV is an Universal Asynchronous Receiver/Transmitter (UART) features that two serial channels are completely independent except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the 16450. Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO mode) to relieve the CPU of excessive software overhead. In FIFO mode each channel is capable of buffering 16 bytes (plus 3-bits of error data per byte in the RCVR FIFO) of data in both the transmitter and receiver. All the FIFO control logic is on-chip to minimize system overhead and maximize system efficiency. Signalling for DMA transfers is done through two pins per channel (TXRDY# and RXRDY#). The RXRDY# function is multiplexed on one pin with the OUT 2# and BAUDOUT functions. The CPU can select these functions through a new register (Alternate Function Register). Each channel performs serial-to-parallel conversion on data characters.
● Dual independent UARTs
● Capable of running all existing 16450 and PC16550D software
● After reset, all registers are identical to the 16450 register set
● Read and write cycle times of 84ns
● Independently controlled transmit, receive, line status and data set interrupts
● MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
● Even, odd or no-parity bit generation and detection
● False start bit detection
● Complete status reporting capabilities
● TRI-STATE® TTL drive for the data and control buses
● Line-break generation and detection
● Loopback controls for communications link fault isolation
● Break, parity, overrun and framing-error simulation
● Full prioritized interrupt system controls
● Can also be reset to 16450 Mode under software control
