The S9S12ZVLS3F0MFM is a signal 16-bit Microcontroller using the 180nm NVM + UHV technology that offers the capability to integrate 40V analog components. The device features enhanced S12Z core and the integration of high-voltage analog modules, including the voltage regulator (VREG) and a Local Interconnect Network (LIN) physical layer. The MC9S12ZVL-Family includes error correction code (ECC) on RAM, FLASH and EEPROM for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase locked loop (IPLL) that improves the EMC performance. The MC9S12ZVL-Family delivers an optimized solution with the integration of several key system components into a single device, optimizing system architecture and achieving significant space savings. The device delivers all the advantages and efficiencies of a 16-bit MCU while retaining the low power consumption, EMC and code-size efficiency advantages currently enjoyed by users of existing S12 families.
● Harvard architecture - parallel data and code access
● 3-Stage pipeline
● 32-bit Wide instruction and data bus
● 32-bit ALU
● 24-bit Addressing (16MB linear address space)
● Phase locked loop (IPLL) frequency multiplier with internal filter
● 1MHz Internal RC oscillator with +/-1.3% accuracy
● 4-20MHz Amplitude controlled pierce oscillator
● Internal COP (watchdog) module
● Analog-to-digital converter (ADC) with 10-bit resolution
● Serial peripheral interface (SPI) module
● Serial communication interface module with interface to internal LIN physical layer transceiver
● On-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard
● 6-channel Timer module (TIM0) with input capture/output compare
● 2-channel Timer module (TIM1) with input capture/output compare
● 8-channel Pulse width modulation module (PWM)
● On-chip voltage regulator (VREG)
● Autonomous periodic interrupt (API), supports cyclic wakeup from Stop mode
● Pins to support 25mA drive strength to VSSX
● Pin to support 20mA drive strength from VDDX (EVDD)
