DESCRIPTION
●The SN65LVDS100, SN65LVDT100, SN65LVDS101, and SN65LVDT101 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage differential signaling
●(LVDS), positive-emitter-coupled logic (PECL), or current-mode logic (CML) input signals at rates up to 2
●Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is
●differential for low radiated emissions and minimal added jitter.
●FEATURES
●• Designed for Signaling Rates(1) ≥ 2 Gbps
●• Total Jitter < 65 ps
●• Low-Power Alternative for the MC100EP16
●• Low 100 ps (Max) Part-To-Part Skew
●• 25 mV of Receiver Input Threshold Hysteresis Over 0-V to 4-V Common-Mode Range
●• Inputs Electrically Compatible With LVPECL, CML, and LVDS Signal Levels
●• 3.3-V Supply Operation
●• LVDT Integrates 110-Ω Terminating Resistor
●• Offered in SOIC and MSOP
●APPLICATIONS
●• 622 MHz Central Office Clock Distribution
●• High-Speed Network Routing
●• Wireless Basestations
●• Low Jitter Clock Repeater
●• Serdes LVPECL Output to FPGA LVDS Input Translator
